/*------------------------------------------------------------------------------
--------------------------------------------------------------------------------
Copyright (c) 2016, Loongson Technology Corporation Limited.

All rights reserved.

Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:

1. Redistributions of source code must retain the above copyright notice, this 
list of conditions and the following disclaimer.

2. Redistributions in binary form must reproduce the above copyright notice, 
this list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.

3. Neither the name of Loongson Technology Corporation Limited nor the names of 
its contributors may be used to endorse or promote products derived from this 
software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 
DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--------------------------------------------------------------------------------
------------------------------------------------------------------------------*/
//apb_uart 0x1f000000-0x1f00ffff
//apb_spi  0x1f010000-0x1f01ffff
//apb_iic  0x1f020000-0x1f02ffff
//apb_gpio 0x1f030000-0x1f03ffff

`include "config.h"

module apb_subsys
(
    input                       clk,
    input                       lcd_clk,
    input                       rst_n,

    input  [`LID            :0] axi_s_awid,
    input  [`Lawaddr     -1 :0] axi_s_awaddr,
    input  [`Lawlen      -1 :0] axi_s_awlen,
    input  [`Lawsize     -1 :0] axi_s_awsize,
    input  [`Lawburst    -1 :0] axi_s_awburst,
    input  [`Lawlock     -1 :0] axi_s_awlock,
    input  [`Lawcache    -1 :0] axi_s_awcache,
    input  [`Lawprot     -1 :0] axi_s_awprot,
    input                       axi_s_awvalid,
    output                      axi_s_awready,
    input  [`Lwdata      -1 :0] axi_s_wdata,
    input  [`Lwstrb      -1 :0] axi_s_wstrb,
    input                       axi_s_wlast,
    input                       axi_s_wvalid,
    output                      axi_s_wready,
    output [`LID            :0] axi_s_bid,
    output [`Lbresp      -1 :0] axi_s_bresp,
    output                      axi_s_bvalid,
    input                       axi_s_bready,
    input  [`LID            :0] axi_s_arid,
    input  [`Laraddr     -1 :0] axi_s_araddr,
    input  [`Larlen      -1 :0] axi_s_arlen,
    input  [`Larsize     -1 :0] axi_s_arsize,
    input  [`Larburst    -1 :0] axi_s_arburst,
    input  [`Larlock     -1 :0] axi_s_arlock,
    input  [`Larcache    -1 :0] axi_s_arcache,
    input  [`Larprot     -1 :0] axi_s_arprot,
    input                       axi_s_arvalid,
    output                      axi_s_arready,
    output [`LID            :0] axi_s_rid,
    output [`Lrdata      -1 :0] axi_s_rdata,
    output [`Lrresp      -1 :0] axi_s_rresp,
    output                      axi_s_rlast,
    output                      axi_s_rvalid,
    input                       axi_s_rready,

    //UART
    input                       uart0_txd_i,
    output                      uart0_txd_o,
    output                      uart0_txd_oe,
    input                       uart0_rxd_i,
    output                      uart0_rxd_o,
    output                      uart0_rxd_oe,
    output                      uart0_rts_o,
    output                      uart0_dtr_o,
    input                       uart0_cts_i,
    input                       uart0_dsr_i,
    input                       uart0_dcd_i,
    input                       uart0_ri_i,
    output                      uart0_int,

    // lcd
    output                      lcd_cs_n,
    output                      lcd_rs, // 0是命令，1是数据
    output                      lcd_wr_n,
    output                      lcd_rd_n,
    output                      lcd_rst_n,
    inout [15:0]                lcd_db,
    output                      lcd_bl, // 背光控制信号(1开启)

    //GPIO(含SPI和I2C引脚复用)
    input [31:0]                io_pads_gpioA_i,
    output [31:0]               io_pads_gpioA_o,
    output [31:0]               io_pads_gpioA_oen,
    output                      gpioA_int,

    //SPI
    output                      qspi0_int,

    //I2C
    output                      i2c0_mst_int
);

parameter                   ADDR_APB = 20,
                            DATA_APB = 8;

wire                        apb_ready_cpu;
wire                        apb_rw_cpu;
wire                        apb_psel_cpu;
wire                        apb_enab_cpu;
wire [ADDR_APB-1 :0]        apb_addr_cpu;
wire [DATA_APB-1:0]         apb_datai_cpu;
wire [DATA_APB-1:0]         apb_datao_cpu;
wire                        apb_clk_cpu;
wire                        apb_reset_n_cpu; 
wire                        apb_word_trans_cpu;
wire                        apb_valid_cpu;
wire  [23:0]                apb_high_24b_rd;
wire  [23:0]                apb_high_24b_wr;


wire                        apb_uart0_req;
wire                        apb_uart0_ack;
wire                        apb_uart0_rw;
wire                        apb_uart0_enab;
wire                        apb_uart0_psel;
wire  [ADDR_APB -1:0]       apb_uart0_addr;
wire  [DATA_APB -1:0]       apb_uart0_datai;
wire  [DATA_APB -1:0]       apb_uart0_datao;

wire                        apb_lcd_req;
wire                        apb_lcd_ack;
wire                        apb_lcd_rw;
wire                        apb_lcd_enab;
wire                        apb_lcd_psel;
wire  [ADDR_APB -1:0]       apb_lcd_addr;
wire  [31:0]                apb_lcd_datai;
wire  [31:0]                apb_lcd_datao;

//SPI
wire                        apb_spi0_ack; 
wire                        apb_spi0_rw; 
wire                        apb_spi0_enab; 
wire                        apb_spi0_psel; 
wire  [ADDR_APB -1:0]       apb_spi0_addr; 
wire  [31:0]                apb_spi0_datai; 
wire  [31:0]                apb_spi0_datao; 
wire                        qspi0_dq_0_oe;
wire                        qspi0_dq_1_oe;
wire                        qspi0_dq_2_oe;
wire                        qspi0_dq_3_oe;

wire                        qspi0_sck_i;
wire                        qspi0_sck_o;
wire                        qspi0_sck_oen;
wire                        qspi0_cs_0_i;
wire                        qspi0_cs_0_o;
wire                        qspi0_cs_0_oen;
wire                        qspi0_dq_0_i;
wire                        qspi0_dq_0_o;
wire                        qspi0_dq_0_oen;
wire                        qspi0_dq_1_i;
wire                        qspi0_dq_1_o;
wire                        qspi0_dq_1_oen;
wire                        qspi0_dq_2_i;
wire                        qspi0_dq_2_o;
wire                        qspi0_dq_2_oen;
wire                        qspi0_dq_3_i;
wire                        qspi0_dq_3_o;
wire                        qspi0_dq_3_oen;

//I2C
wire                        apb_i2c0_ack; 
wire                        apb_i2c0_rw; 
wire                        apb_i2c0_enab; 
wire                        apb_i2c0_psel; 
wire  [ADDR_APB -1:0]       apb_i2c0_addr; 
wire  [31:0]                apb_i2c0_datai; 
wire  [31:0]                apb_i2c0_datao; 

wire                        i2c0_scl_i;
wire                        i2c0_scl_o;
wire                        i2c0_scl_oen;
wire                        i2c0_sda_i;
wire                        i2c0_sda_o;
wire                        i2c0_sda_oen;

wire                        apb_gpioa_ack; 
wire                        apb_gpioa_rw; 
wire                        apb_gpioa_enab; 
wire                        apb_gpioa_psel; 
wire  [ADDR_APB -1:0]       apb_gpioa_addr; 
wire  [31:0]                apb_gpioa_datai; 
wire  [31:0]                apb_gpioa_datao;

wire [31:0]                 gpioA_i;
wire [31:0]                 gpioA_o;
wire [31:0]                 gpioA_oe;
wire [31:0]                 gpioA_in_sync;
wire [31:0]                 gpioA_iof;

axi2apb_bridge AA_axi2apb_bridge_cpu 
(
    .clk                (clk                ),
    .rst_n              (rst_n              ),

    // axi接口
    .axi_s_awid         (axi_s_awid         ),
    .axi_s_awaddr       (axi_s_awaddr       ),
    .axi_s_awlen        (axi_s_awlen        ),
    .axi_s_awsize       (axi_s_awsize       ),
    .axi_s_awburst      (axi_s_awburst      ),
    .axi_s_awlock       (axi_s_awlock       ),
    .axi_s_awcache      (axi_s_awcache      ),
    .axi_s_awprot       (axi_s_awprot       ),
    .axi_s_awvalid      (axi_s_awvalid      ),
    .axi_s_awready      (axi_s_awready      ),
    .axi_s_wid          (axi_s_awid         ),//在AXI4总线中wid接入awid即可
    .axi_s_wdata        (axi_s_wdata        ),
    .axi_s_wstrb        (axi_s_wstrb        ),
    .axi_s_wlast        (axi_s_wlast        ),
    .axi_s_wvalid       (axi_s_wvalid       ),
    .axi_s_wready       (axi_s_wready       ),
    .axi_s_bid          (axi_s_bid          ),
    .axi_s_bresp        (axi_s_bresp        ),
    .axi_s_bvalid       (axi_s_bvalid       ),
    .axi_s_bready       (axi_s_bready       ),
    .axi_s_arid         (axi_s_arid         ),
    .axi_s_araddr       (axi_s_araddr       ),
    .axi_s_arlen        (axi_s_arlen        ),
    .axi_s_arsize       (axi_s_arsize       ),
    .axi_s_arburst      (axi_s_arburst      ),
    .axi_s_arlock       (axi_s_arlock       ),
    .axi_s_arcache      (axi_s_arcache      ),
    .axi_s_arprot       (axi_s_arprot       ),
    .axi_s_arvalid      (axi_s_arvalid      ),
    .axi_s_arready      (axi_s_arready      ),
    .axi_s_rid          (axi_s_rid          ),
    .axi_s_rdata        (axi_s_rdata        ),
    .axi_s_rresp        (axi_s_rresp        ),
    .axi_s_rlast        (axi_s_rlast        ),
    .axi_s_rvalid       (axi_s_rvalid       ),
    .axi_s_rready       (axi_s_rready       ),

    //控制信号，用于处理32位的apb传输
    .apb_word_trans     (apb_word_trans_cpu ),//开启apb32位模式
    .apb_high_24b_rd    (apb_high_24b_rd    ),//PRDATA的高24位
    .apb_high_24b_wr    (apb_high_24b_wr    ),//PWDATA的高24位
    .apb_valid_cpu      (apb_valid_cpu      ),//apb请求有效
    .cpu_grant          (1'b1               ),//axi输入有效

    //apb接口
    .apb_clk            (apb_clk_cpu        ),//同频时钟，就是clk
    .apb_reset_n        (apb_reset_n_cpu    ),//rst_n

    .reg_psel           (apb_psel_cpu       ),//PSEL
    .reg_enable         (apb_enab_cpu       ),//PENABLE
    .reg_rw             (apb_rw_cpu         ),//PWRITE
    .reg_addr           (apb_addr_cpu       ),//PADDR
    .reg_datai          (apb_datai_cpu      ),//PWDATA
    .reg_datao          (apb_datao_cpu      ),//PRDATA
    .reg_ready_1        (apb_ready_cpu      ) //PREADY
);

apb_mux4 u_apb_mux4
(
    .clk                (clk                ),
    .rst_n              (rst_n              ),

    .apb_ack_cpu        (apb_ready_cpu      ),//PREADY
    .apb_rw_cpu         (apb_rw_cpu         ),//PWRITE
    .apb_addr_cpu       (apb_addr_cpu       ),//PADDR
    .apb_psel_cpu       (apb_psel_cpu       ),//PSEL
    .apb_enab_cpu       (apb_enab_cpu       ),//PENABLE
    .apb_datai_cpu      (apb_datai_cpu      ),//PWDATA
    .apb_datao_cpu      (apb_datao_cpu      ),//PRDATA
    .apb_high_24b_rd    (apb_high_24b_rd    ),
    .apb_high_24b_wr    (apb_high_24b_wr    ),
    .apb_word_trans_cpu (apb_word_trans_cpu ),

    .apb0_req           (                   ),
    .apb0_ack           (apb_uart0_ack      ),//PREADY
    .apb0_rw            (apb_uart0_rw       ),//PWRITE
    .apb0_psel          (apb_uart0_psel     ),//PSEL
    .apb0_enab          (apb_uart0_enab     ),//PENABLE
    .apb0_addr          (apb_uart0_addr     ),//PADDR
    .apb0_datai         (apb_uart0_datai    ),//PWDATA
    .apb0_datao         (apb_uart0_datao    ),//PRDATA

    .apb1_req           (                   ),
    .apb1_ack           (apb_spi0_ack       ),//PREADY
    .apb1_rw            (apb_spi0_rw        ),//PWRITE
    .apb1_psel          (apb_spi0_psel      ),//PSEL
    .apb1_enab          (apb_spi0_enab      ),//PENABLE
    .apb1_addr          (apb_spi0_addr      ),//PADDR
    .apb1_datai         (apb_spi0_datai     ),//PWDATA
    .apb1_datao         (apb_spi0_datao     ),//PRDATA

    .apb2_req           (                   ),
    .apb2_ack           (apb_i2c0_ack       ),//PREADY
    .apb2_rw            (apb_i2c0_rw        ),//PWRITE
    .apb2_psel          (apb_i2c0_psel      ),//PSEL
    .apb2_enab          (apb_i2c0_enab      ),//PENABLE
    .apb2_addr          (apb_i2c0_addr      ),//PADDR
    .apb2_datai         (apb_i2c0_datai     ),//PWDATA
    .apb2_datao         (apb_i2c0_datao     ),//PRDATA

    .apb3_req           (                    ),
    .apb3_ack           (apb_gpioa_ack       ),//PREADY
    .apb3_rw            (apb_gpioa_rw        ),//PWRITE
    .apb3_psel          (apb_gpioa_psel      ),//PSEL
    .apb3_enab          (apb_gpioa_enab      ),//PENABLE
    .apb3_addr          (apb_gpioa_addr      ),//PADDR
    .apb3_datai         (apb_gpioa_datai     ),//PWDATA
    .apb3_datao         (apb_gpioa_datao     ),//PRDATA

    .apb4_req           (                   ),
    .apb4_ack           (apb_lcd_ack        ),//PREADY
    .apb4_rw            (apb_lcd_rw         ),//PWRITE
    .apb4_psel          (apb_lcd_psel       ),//PSEL
    .apb4_enab          (apb_lcd_enab       ),//PENABLE
    .apb4_addr          (apb_lcd_addr       ),//PADDR
    .apb4_datai         (apb_lcd_datai      ),//PWDATA
    .apb4_datao         (apb_lcd_datao      ) //PRDATA
);

//uart0
assign apb_uart0_ack = apb_uart0_enab;
UART_TOP uart0
(
    .PCLK              (clk              ),
    .clk_carrier       (1'b0             ),
    .PRST_             (rst_n            ),
    .PSEL              (apb_uart0_psel   ),
    .PENABLE           (apb_uart0_enab   ),
    .PADDR             (apb_uart0_addr[7:0] ),
    .PWRITE            (apb_uart0_rw     ),
    .PWDATA            (apb_uart0_datai  ),
    .URT_PRDATA        (apb_uart0_datao  ),
    .INT               (uart0_int         ),
    .TXD_o             (uart0_txd_o       ),
    .TXD_i             (uart0_txd_i       ),
    .TXD_oe            (uart0_txd_oe      ),
    .RXD_o             (uart0_rxd_o       ),
    .RXD_i             (uart0_rxd_i       ),
    .RXD_oe            (uart0_rxd_oe      ),
    .RTS               (uart0_rts_o       ),
    .CTS               (uart0_cts_i       ),
    .DSR               (uart0_dsr_i       ),
    .DCD               (uart0_dcd_i       ),
    .DTR               (uart0_dtr_o       ),
    .RI                (uart0_ri_i        )
);

//lcd
assign apb_lcd_ack = apb_lcd_enab;
apb_lcd lcd (
    .HCLK          (clk             ),
    .HRESETn       (rst_n           ),
    .PADDR         (apb_lcd_addr    ),
    .PWDATA        (apb_lcd_datai   ),
    .PWRITE        (apb_lcd_rw      ),
    .PSEL          (apb_lcd_psel    ),
    .PENABLE       (apb_lcd_enab    ),
    .PRDATA        (apb_lcd_datao   ),
    .PSLVERR       (),

    .lcd_clk       (lcd_clk         ),
    .lcd_cs_n      (lcd_cs_n        ),
    .lcd_rs        (lcd_rs          ),
    .lcd_wr_n      (lcd_wr_n        ),
    .lcd_rd_n      (lcd_rd_n        ),
    .lcd_rst_n     (lcd_rst_n       ),
    .lcd_db        (lcd_db          ),
    .lcd_bl        (lcd_bl          )
);

apb_spi_master #(
  .APB_ADDR_WIDTH (ADDR_APB)
) apb_spi0 (
    .HCLK          (clk             ),
    .HRESETn       (rst_n           ),
    .PADDR         (apb_spi0_addr   ),
    .PWDATA        (apb_spi0_datai  ),
    .PWRITE        (apb_spi0_rw     ),
    .PSEL          (apb_spi0_psel   ),
    .PENABLE       (apb_spi0_enab   ),
    .PRDATA        (apb_spi0_datao  ),
    .PREADY        (apb_spi0_ack    ),
    .PSLVERR       (),

    .events_o      (qspi0_int),

    .spi_clk       (qspi0_sck_o),
    .spi_csn0      (qspi0_cs_0_o),
    .spi_csn1      (),
    .spi_csn2      (),
    .spi_csn3      (),
    .spi_sdo0      (qspi0_dq_0_o),
    .spi_sdo1      (qspi0_dq_1_o),
    .spi_sdo2      (qspi0_dq_2_o),
    .spi_sdo3      (qspi0_dq_3_o),
    .spi_oe0       (qspi0_dq_0_oe),
    .spi_oe1       (qspi0_dq_1_oe),
    .spi_oe2       (qspi0_dq_2_oe),
    .spi_oe3       (qspi0_dq_3_oe),
    .spi_sdi0      (qspi0_dq_0_i),
    .spi_sdi1      (qspi0_dq_1_i),
    .spi_sdi2      (qspi0_dq_2_i),
    .spi_sdi3      (qspi0_dq_3_i)
);
assign qspi0_dq_0_oen = ~qspi0_dq_0_oe;
assign qspi0_dq_1_oen = ~qspi0_dq_1_oe;
assign qspi0_dq_2_oen = ~qspi0_dq_2_oe;
assign qspi0_dq_3_oen = ~qspi0_dq_3_oe;
assign qspi0_sck_oen  = 1'b0;
assign qspi0_cs_0_oen  = 1'b0;

apb_i2c #(
  .APB_ADDR_WIDTH (ADDR_APB) 
) apb_i2c0 (
    .HCLK          (clk             ),
    .HRESETn       (rst_n           ),
    .PADDR         (apb_i2c0_addr   ),
    .PWDATA        (apb_i2c0_datai  ),
    .PWRITE        (apb_i2c0_rw     ),
    .PSEL          (apb_i2c0_psel   ),
    .PENABLE       (apb_i2c0_enab   ),
    .PRDATA        (apb_i2c0_datao  ),
    .PREADY        (apb_i2c0_ack    ),
    .PSLVERR       (),

    .interrupt_o   (i2c0_mst_int),
    .scl_pad_i     (i2c0_scl_i),
    .scl_pad_o     (i2c0_scl_o),
    .scl_padoen_o  (i2c0_scl_oen),
    .sda_pad_i     (i2c0_sda_i),
    .sda_pad_o     (i2c0_sda_o),
    .sda_padoen_o  (i2c0_sda_oen)
);

apb_gpio # (
  .APB_ADDR_WIDTH (ADDR_APB)
) apb_gpioA (
    .HCLK           (clk              ),
    .HRESETn        (rst_n            ),
    .PADDR          (apb_gpioa_addr   ),
    .PWDATA         (apb_gpioa_datai  ),
    .PWRITE         (apb_gpioa_rw     ),
    .PSEL           (apb_gpioa_psel   ),
    .PENABLE        (apb_gpioa_enab   ),
    .PRDATA         (apb_gpioa_datao  ),
    .PREADY         (apb_gpioa_ack    ),
    .PSLVERR        (),

    .gpio_in        (gpioA_i),
    .gpio_in_sync   (gpioA_in_sync),
    .gpio_out       (gpioA_o),
    .gpio_dir       (gpioA_oe),
    .gpio_padcfg    (),
    .gpio_iof       (gpioA_iof),
    .interrupt      (gpioA_int)
);

// The GPIOA IOF SET 
assign  io_pads_gpioA_oen[0]        =  gpioA_iof[0]   ?   qspi0_sck_oen   : (~gpioA_oe[0]);
assign  io_pads_gpioA_oen[1]        =  gpioA_iof[1]   ?   qspi0_cs_0_oen  : (~gpioA_oe[1]);
assign  io_pads_gpioA_oen[2]        =  gpioA_iof[2]   ?   qspi0_dq_0_oen  : (~gpioA_oe[2]);
assign  io_pads_gpioA_oen[3]        =  gpioA_iof[3]   ?   qspi0_dq_1_oen  : (~gpioA_oe[3]);
assign  io_pads_gpioA_oen[4]        =  gpioA_iof[4]   ?   qspi0_dq_2_oen  : (~gpioA_oe[4]);
assign  io_pads_gpioA_oen[5]        =  gpioA_iof[5]   ?   qspi0_dq_3_oen  : (~gpioA_oe[5]);
assign  io_pads_gpioA_oen[6]        =  gpioA_iof[6]   ?   i2c0_scl_oen    : (~gpioA_oe[6]);
assign  io_pads_gpioA_oen[7]        =  gpioA_iof[7]   ?   i2c0_sda_oen    : (~gpioA_oe[7]);
assign  io_pads_gpioA_oen[31:8]     =  ~gpioA_oe[31:8];

assign  io_pads_gpioA_o[0]          =  gpioA_iof[0]   ?   qspi0_sck_o     : gpioA_o[0];
assign  io_pads_gpioA_o[1]          =  gpioA_iof[1]   ?   qspi0_cs_0_o    : gpioA_o[1];
assign  io_pads_gpioA_o[2]          =  gpioA_iof[2]   ?   qspi0_dq_0_o    : gpioA_o[2];
assign  io_pads_gpioA_o[3]          =  gpioA_iof[3]   ?   qspi0_dq_1_o    : gpioA_o[3];
assign  io_pads_gpioA_o[4]          =  gpioA_iof[4]   ?   qspi0_dq_2_o    : gpioA_o[4];
assign  io_pads_gpioA_o[5]          =  gpioA_iof[5]   ?   qspi0_dq_3_o    : gpioA_o[5];
assign  io_pads_gpioA_o[6]          =  gpioA_iof[6]   ?   i2c0_scl_o      : gpioA_o[6];
assign  io_pads_gpioA_o[7]          =  gpioA_iof[7]   ?   i2c0_sda_o      : gpioA_o[7];
assign  io_pads_gpioA_o[31:8]       =  gpioA_o[31:8];

assign  gpioA_i                     =  io_pads_gpioA_i;
assign  qspi0_sck_i                 =  gpioA_in_sync[0];
assign  qspi0_cs_0_i                =  gpioA_in_sync[1];
assign  qspi0_dq_0_i                =  gpioA_in_sync[2];
assign  qspi0_dq_1_i                =  gpioA_in_sync[3];
assign  qspi0_dq_2_i                =  gpioA_in_sync[4];
assign  qspi0_dq_3_i                =  gpioA_in_sync[5];
assign  i2c0_scl_i                  =  gpioA_in_sync[6];
assign  i2c0_sda_i                  =  gpioA_in_sync[7];


endmodule


